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PRELIMINARY SPECIFICATION
KS0708
INTRODUCTION
64COM/128SEG DRIVE FOR DOT MATRIX LCD
KS0708 is a single-chip LCD driver LSI for liquid crystal dot-matrix graphic display systems. It incorporates 192 driver circuit for 64 commom and 128 segment and 64x128-bit bit-map RAM. It is capable of interfacing with the microprocessor, accepting 8-bit parallel display data directly from it, and storing data in an onechip Display Data RAM. And it generates internal signals for using LCD driving independent of microprocessor clock.
FEATURES
U 64-Channel COMMON & 128-Channel SEGMENT Driver for DOT matrix LCD U On-chip display data RAM : 64 X 128 = 8192bits U Display data is stored in display data RAM from MPU - RAM bit data : ON(1), OFF(0) U Internal timing generator circuit for dynamic display U 8-bit parallel bi-directional data bus U Applicable LCD duty : 1/64 U Power supply voltages : Power supply voltage range : 4.5 ~ 5.5 V(VDD) LCD Driving voltage range : 8.0 ~ 17.0 V(VLCD = VDD - VEE) U Wide operating temperature range : Ta = -30 E ~ 85E U High Voltage CMOS process U Package : available bumped chip
M/M-96-D001 97-09-19
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PRELIMINARY SPECIFICATION
KS0708
BLOCK DIAGRAM
64COM/128SEG DRIVE FOR DOT MATRIX LCD
C1 ... C32
...
S1 S2
...
...
S63 S64 S65 S66
...
...
S127 S128 C33...C64
...
VDD V0 V1 V2 V3 V4 V5 VEE VSS FS
32 CHANNEL COMMON
64 CHANNEL SEGMENT DRIVER
64 CHANNEL SEGMENT DRIVER
32 CHANNEL COMMON DRIVER
32BIT
SHIFT REG
32BIT
SHIFT REG
SHL PCLK2
64-BIT DATA LATCH
DISPLAY TIMING GENERATOR CIRCUIT
PAGE & LINE Decoder
64-BIT DATA LATCH
PAGE & LINE Decoder
C CR R
OSCILLATOR
DISPLAY DATA RAM 64 X 64 = 4,096 BITS
DISPLAY DATA RAM 64 X 64 = 4,096 BITS
Column Decoder ADC
Column Decoder
RAM Address register
RAM Address register
STATUS REGISTER
INSTRUCTION DECODER
INSTRUCTION DECODER
ISTATUS REGISTER
I/O BUFFER
I/O REGISTER
I/O BUFFER
4 RW RS E RESETB CS2B CS1B DB0 ~ DB7
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PRELIMINARY SPECIFICATION
KS0708
PAD CONFIGURATION
64COM/128SEG DRIVE FOR DOT MATRIX LCD
218 219 Y (TOP VIEW) (0,0) X
86 85
..
..
54 53
KS0708
250 1
SIZE ITEM CHIP SIZE PAD PITCH PAD NO... X 1 ~ 53 BUMPED PAD SIZE 54 ~ 85 86 ~ 218 219 ~ 250 BUMPED PAD HEIGHT ALL PAD 56 140 56 140 18 3/4 3 12590 90(MIN) 140 56 140 56 im Y 3630 UNIT
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
PAD LOCATION
PAD NO.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
PAD NAME
DUMMY DUMMY DUMMY VEE VEE VEE V5 V5 V5 V4 V4 V4 V3 V3 V3 V2 V2 V2 V1 V1 V1 V0 V0 V0 VDD VDD VDD VSS VSS VSS PCLK2 FS SHL ADC CS2B C CR R DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RS RW E CS1B RESETB DUMMY DUMMY C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
X
-6115 -6025 -5935 -5477 -5257 -5037 -4817 -4597 -4377 -4157 -3937 -3717 -3497 -3277 -3057 -2837 -2617 -2397 -2177 -1957 -1737 -1517 -1297 -1077 -857 -637 -417 -197 23 243 463 683 903 1123 1343 1563 1783 2003 2175 2467 2759 3051 3343 3635 3927 4219 4559 4779 4999 5219 5439 6025 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115
Y
-1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1386.5 -1296.5 -1206.5 -1116.5 -1026.5 -936.5 -846.5 -756.5 -666.5 -576.5
PAD NO.
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
PAD NAME
C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 DUMMY DUMMY S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39
X
6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6025 5715 5625 5535 5445 5355 5265 5175 5085 4995 4905 4815 4725 4635 4545 4455 4365 4275 4185 4095 4005 3915 3825 3735 3645 3555 3465 3375 3285 3195 3105 3015 2925 2835 2745 2655 2565 2475 2385 2295
Y
-486.5 -396.5 -306.5 -216.5 -126.5 -36.5 53.5 143.5 233.5 323.5 413.5 503.5 593.5 683.5 773.5 863.5 953.5 1043.5 1133.5 1223.5 1313.5 1403.5 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635
PAD NO.
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189
PAD NAME
S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102
X
2205 2115 2025 1935 1845 1755 1665 1575 1485 1395 1305 1215 1125 1035 945 855 765 675 585 495 405 315 225 135 45 -45 -135 -225 -315 -405 -495 -585 -675 -765 -855 -945 -1035 -1125 -1215 -1305 -1395 -1485 -1575 -1665 -1755 -1845 -1935 -2025 -2115 -2205 -2295 -2385 -2475 -2565 -2655 -2745 -2835 -2925 -3015 -3105 -3195 -3285 -3375
Y
1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635
PAD NO.
190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
PAD NAME
S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 DUMMY DUMMY DUMMY C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33
X
-3465 -3555 -3645 -3735 -3825 -3915 -4005 -4095 -4185 -4275 -4365 -4456 -4545 -4635 -4725 -4815 -4905 -4995 -5085 -5175 -5265 -5355 -5445 -5535 -5625 -5715 -5935 -6025 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115
Y
1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1403.5 1313.5 1223.5 1133.5 1043.5 953.5 863.5 773.5 683.5 593.5 503.5 413.5 323.5 233.5 143.5 53.5 -36.5 -126.5 -216.5 -306.5 -396.5 -486.5 -576.5 -666.5 -756.5 -846.5 -936.5 -1026.5 -1116.5 -1206.5 -1296.5 -1386.5
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PRELIMINARY SPECIFICATION
KS0708
PAD DESCRIPTION Power Supply Name
VDD VSS VEE V0, V1 V2, V3 V4, V5
64COM/128SEG DRIVE FOR DOT MATRIX LCD
I/O
Supply Supply Supply Supply Power supply Ground For LCD driver circuit
Description
LCD driver supply voltages The voltages must satisfy the following relationship VDD A V0 A V1 A V2 A V3 A V4 A V5 A VEE
Oscillator
Name I/O RC Oscillator ) Internal clock KS0708 R C CR R O I ) External clock O KS0708 R OPEN CR External clock C Open CR Rf Cf C Description
Rf : 47k O Cf : 20pF
Frequency Selection When the frame frequency is 70Hz, the oscillation frequency should be as following table. FS I FS 1 0 - Oscillation Frequency fose = 430 kHz fosc = 215kHz
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
Microprocessor Interface
Name CS1B CS2B RS I/O I I I Description First Chip(S1 ~ S64) Select input. Data input/output is enabled via E, RS, RW, and DB[0:7]when CS1B = Low. Second Chip(S65 ~ S128) Select input. Data input/output is enabled via E, RS, RW, and DB[0:7] when CS2B = Low. Register Selection - HIGH : The data in DB[7:0] is display data - LOW : The data in DB[7:0] is control data Read or Write RW RW I H L Description Data appears at DB< 7:0 > when E = High. Display data DB < 7:0 > can be written at falling edge of E.
Enable signal. RW E H L Description Read data in DB< 7:0 > appears the while E is high level. Display data DB < 7:0 > is latched at falling edge of E.
DB0 ~ DB7
I/0
Data Bus [0 ~ 7] - Bi-directional data bus
Reset
Name RESETB I/O I Description Reset input - Chip is initialized when RESETB is LOW
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
LCD Driver Outputs
Name C1 ~ C64 S1 ~ S128
I/O O O LCD driver common output LCD driver segment output
Description
Phase of internal shift clock (CLK2) PCLK2 PCLK2 I 0 1 Phase of Internal Shift Clock (CLK2) Data shift at the falling edge of CLK2 Data shift at the rising edge of CLK2
Address Control signal of Y address counter. ADC ADC I H L Segment output direction S1 ae S2 ....S63 ae S65 ae S66 ....S127 ae S128 S64 ae S63 ....S2 ae S1 ae S128 ae S127 ....S66 ae S65
Selection of data shift direction SHL SHL I H L Data shift direction C1 ae C2 ae C3 .... C62 ae C63 ae C64 C64 ae C63 ae C62 .... C3 ae C2 ae C1
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PRELIMINARY SPECIFICATION
KS0708
FUNCTIONAL DESCRIPTION Chip Select input
64COM/128SEG DRIVE FOR DOT MATRIX LCD
The KS0708 has two chip select pin, CS1B and CS2B. It can interface with a mircoprocessor when these pins(CS1B or CS2B)is Low. When both of these pins are set to High, DB0 to DB7 are high impedance and RS, RW, and E inputs are disabled. CS1B pin controls the display status of S1 to S64, and CS2B does that of S65 to S128. When CS1B and CS2B are Low at the same time, it is impossible to execute read operation. Therefore one of CS1B or CS2B should be set to Low((CS1B = H& CS2B = L)or (CS1B = L & CS2B = H)) in read operation. The RESETB signal is entered independet of the status of Chip Select.
Read Operation CS1B H L H L CS2B H H L L CS1 X U X CS2 X X U -
Write Operation CS1 X U X U CS2 X X U U
( - : Not Recommended, U : Operation, X : No Operation) Table 1. Relationship between Chip Select pins and Read/Write Operation
Microprocessor Interface
KS0708 transfers 8-bit parallel in either direction between the controlling microprocessor and the KS0708 through the 8-bit I/O buffer(DB0 TO DB7). RS, RW and E identify the type of parallel data transfer to be made as shown in table 2.
RS H H L L
RW H L H L
Description Display data read Display data write Status read Writes to internal register (Instruction) Table 2. Microprocessor Interface
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
Busy flag
Busy flag indicates whether KS0708 is operating or not. When busy flag is high, KS0708 is in internal operation. When low, KS0708 can accept the data or instruction. DB7 indicates busy flag of the KS0708.
E
BUSY FLAG
TBUSY A 4/ fosc
Figure 1. Busy timing
Display Timing Generator Circuit
This section explains how the timing generation circuit operates. - Signal generation to display start line counter and display data latch circuit. - The display clock(CLK2) generates a clock to the line counter. The display start line address of the display RAM is synchronized with the display clock. 128-bit display data is latched by the display data latch circuit in synchronization with the display clock and output to the segment LCD drive output pin. - LCD AC signal(M) generation.
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
Display Data RAM
The Display Data RAM stores pixel data for the LCD. It is a 128-column x 64-row addressable array as shown in Figure 3. The 64 rows are divided into 8 pages of 8 lines. Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The microprocessor reads from and writes to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written to RAM at the same time as data is being displayed, without causing the LCD to flick.
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
1 1 1 1 1 1 1 0
0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0
0 1 0 0 0 1 0 0
1 0 0 0 0 0 1 0
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 ( LCD Panel )
( Display Data RAM ) Figure 2. RAM-to-LCD data transfer
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
SEGMENT OUTPUT(S1~S64) Page address Line address S 1 SS 23 S 4 ...... S 6 1 SS 66 23 S 6 4 DATA BUS
SEGMENT OUTPUT(S65~S128) SSS 666 567 S 6 8 S 1 2 5 S 1 2 6 S 1 2 7 S 1 2 8 Line address Page address
......
0000
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 38 39
......
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
......
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
000
001
......
......
001
010
......
......
010
011
......
......
011
100
......
......
100
101
40 41 42 43 44 45 46 47
......
......
101
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
SEGMENT OUTPUT(S1~S64) Page address Line address S 1 SS 23 S 4 ...... S 6 1 SS 66 23 S 6 4 DATA BUS
SEGMENT OUTPUT(S65~S128) SSS 666 567 S 6 8 S 1 2 5 S 1 2 6 S 1 2 7 S 1 2 8 Line address Page address
......
110
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 0 1 2 4
......
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 6 0 3 6 1 2 6 2 1 6 3 0 0 1 2 4
......
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 6 0 3 6 1 2 6 2 1 6 3 0 1
110
111
......
......
111
......
......
ADC 0 6 3 6 2 6 1 6 0 ...... 6 3 6 2 6 1 6 0 ...... 0
ADC
Column address Chip Select (CS1B)
Column address Chip Select (CS2B)
Figure 3. Display Data RAM
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
MPU signal RS RW E DB[7:0] Internal signal WR Input Buffer Column Address Page Address RAM
K N D(N) D(N+1) D(N+2) D(N+3) D(N+4) N D(N) D(N+1) D(N+2) D(N+3) D(N+4) D(N+5)
N
N+1
N+2
N+3
N+4
N+5
Preset Set Page Address => K
D(N) D(N+1) D(N+2) D(N+3) D(N+4)
Figure 4. Write Timing MPU signal RS RW E DB[7:0]
N Dummy D(N) D(N+1) D(N+2) D(N+3)
Internal signal WR RD Output Buffer Column Address Page Address
Dummy D(N) D(N+1) D(N+2) D(N+3) D(N+4)
N
N+1
N+2
N+3
N+4
N+5
Preset
K
Set Page Address => K Figure 5. Read timing
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
Data Tramsfer
To match the timing of the display data RAM and registers to that of the controlling microprocessor, KS0708 uses an internal data bus and bus buffer. When the microprocessor reads the contents of display data RAM, the data for the initial read cycle is first stored inthe bus buffer (dummy read cycle). On the next read cycle, the data is read from the bus buffer onto the microprocessor bus. At the same time, the next block of data is transferred from RAM to the bus buffer. Otherwise, when the microprocessor write data to display data RAM. the data is written to RAM atfer the falling edge of aE. Therefore, it is necessary to check Busy Flag to write or read the next data. (refer to Figure4, 5)
Page Address Register
The 3-bit Page Address register provides the page address to display data RAM (refer to Figure 3). The microprocessor issues Set Page Address instruction to change the page and to access another page.
Column Address Counter
The column address counter is a 6-bit presettable counter that provides column address to display data RAM (refer to Figure 3). It is incremented by 1 automatically after execution of each Read/Write Data instruction. The column address counter loops the values 0 to 127, and it is independent of page address register. The ADC pin is issued to change the relationship between RAM Column address and display segment output.
Display Start Line Register
The display start line register stores the line address of display data RAM that corresponds to the first (normally the top) line(COM1) of liquid crystal display(LCD) panel. See Figure 3. When displaying contents in display data RAM on the LCD panel, 6-bit data(DB[5:0]) of the Set Display Start Line is latched in display start line register. Latched data are transferred to the line address counter just before COM1 is active High, presetting the line address counter. The line counter is then incremented on the display latch clock signal once for every display line. It is used for vertical scrolling of the liquid crystal display screen.
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PRELIMINARY SPECIFICATION
KS0708
LCD Driver
64COM/128SEG DRIVE FOR DOT MATRIX LCD
LCD driver circuit has 192 outputs of 128 segment outputs, 64 common outputs for LCD driving. Each common output has a shift register. LCD driving output voltage is determined by the combination of display data and internal AC signal. Display Data 0 Common output V1 V4 V5 1 Display OFF V0 Segment output V2 V3 V0 V5 V2 or V3
Table 4. Relationship between data for each input signal and the LCD drive output.
Reset Circuit
Reset function can initialize system by setting RESETB terminal at Low level. When RESETB becomes low, following procedure occurs. - Display start line : 0(First) - Display ON/OFF : OFF While RESETB is in Low level, no instruction except Status Read can be accepted. Reset status appears at DB4. Refers to Read Status of (c)INSTRUCTION DESCRIPTION (c). The conditions of power supply at initial power up are shown in table 3. Item Reset time Rise time Symbol tRESETB tr Min 1.0 Typ Max 200 Unit us ns
Table 5. Power supply initial Conditions.
tRESETB
VDD RESETB
tr 0.7VDD 0.3VDD
Figure 6. Reset Timing
M/M-96-D001 97-09-19 15
PRELIMINARY SPECIFICATION
KS0708
INSTRUCTION DESCRIPTION
64COM/128SEG DRIVE FOR DOT MATRIX LCD
Instruction Table
Instruction
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Function
Reads data (DB[0:7]) from display data RAM to the data bus. Writes data(DB[0:7]) into display data RAM. After writing instruction, column address is incremented by 1 automatically. Reads status BUSY -0 : Ready -1 : In operation ON/OFF -0 : Display ON -1 : Display OFF RESET -0 : Normal -1 : Reset Sets the Column address at the Column address counter Indicates the display data RAM displayed at the top of the screen. Sets the Page address at the Page address register. Controls the display on or off. Internal status and display RAM data is not affected. L:OFF, H:ON
Read display data
1
1
Read data
Write display data
1
0
Write data
Status Read
0
1
BUSY
0
ON/ OFF
RESET
0
0
0
0
Set Column Address
0
0
0
1
Column address (0 ~ 63)
Set Display Start Line
0
0
1
1
Display Start Line (0 ~ 63)
Set Page Address
0
0
1
0
1
1
1
Page (0 ~ 7)
Display ON/OFF
0
0
0
0
1
1
1
1
1
0/1
M/M-96-D001 97-09-19
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PRELIMINARY SPECIFICATION
KS0708
Instructions a Read Display Data
64COM/128SEG DRIVE FOR DOT MATRIX LCD
Reads 8-bit data display data RAM area specified by column address and page address. As the column address is incremented by 1 automatically after each read operation, the microprocessor can continue to read data of multiple words. RS 1 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read data
a Write Display Data
Writes 8-bit data in display data RAM. As the column address is incremented by 1 automatically after each write operation, the microprocessor can continue to write data of multiple words. RS 1 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write data
a Read Status
Indicates the internal status conditions of the device to the microprocessor. RS 0 RW 1 DB7 BUSY DB6 0 DB5 ON/OFF DB4 RESET DB3 0 DB2 0 DB1 0 DB0 0
Flag BUSY ON/OFF RESET
Description The device is busy due to internal operation or reset. Any instruction is rejected until BUSY goes Low. Indicates whether the display is on or off. When goes Low, the display is on. When goes High, the display is off. This is the opposite of Display ON/OFF instruction. Indicates the initialization is in progress by RESETB signal. When Low, the chip is in active. When High, the chip is being reset.
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
a Set Page Address
Sets the page address of display RAM from the microprocessor into the page address register. Along with Column address register, Page address register assigns the address of the display RAM to be written to or read from display data. Changing the address doesn t affect the display status. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 1 DB2 X2 DB1 X1 DB0 X0
X2 0 0 : 1
X1 0 0 : 1
X0 0 1 : 1
Page 0 1 : 7
a Set Column Address
Sets the Column address of display RAM from the microprocessor into the Column address register. When the microprocessor reads or writes display data to or from display RAM, the address are automatically incremented. RS 0 RW 0 DB7 0 DB6 1 DB5 Y5 DB4 Y4 DB3 Y3 DB2 Y2 DB1 Y1 DB0 Y0
Y5 0 0 : 1 1
Y4 0 0 : 1 1
Y3 0 0 : 1 1
Y2 0 0 : 1 1
Y1 0 0 : 1 1
Y0 0 1 : 0 1
Column address 0 1 : 62 63
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
a Set Display Start Line
Sets the line address of display RAM to determine the display start line. The display data on the specified line of the display RAM is displayed at the top row COM1 of LCD panel. It is followed by the higher number of lines in ascending order corresponding to the determined duty cycle. When this instruction changes the display start line address, the LCD panel can be scrolled. RS 0 RW 0 DB7 1 DB6 1 DB5 Z5 DB4 Z4 DB3 Z3 DB2 Z2 DB0 Z1 DB0 Z0
Z5 0 0 : 1 1
Z4 0 0 : 1 1
Z3 0 0 : 1 1
Z2 0 0 : 1 1
Z1 0 0 : 1 1
Z0 0 1 : 0 1
Line address 0 1 : 62 63
a Display ON/OFF
Turns the display ON or OFF. RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB0 1 DB0 D0
D0 = 1 : Display ON D0 = 0 : Display OFF
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
a APPLICATION DIAGRAM1 (ADC = H, SHL = H)
COM1 . . COM32
LCD Panel (64 x 128)
SEG1 SEG2 .... SEG127 SEG128
COM33 . . COM64
S1
C32 . . . . C1
S2 . . . S127
S128
C64 . . . . C33
KS0708
(Bottom View)
CS2B VDD V0 V1 V2 V3 V4 V5 VEE E R/W RS DB[0:7] RESETB
CS1B CS1B
VDD 12 V0 V1 V2
CS2B E R/W RS DB[0:7] RESETB
V3 V4
MPU V5
VEE Figure 7. Application Diagram1
M/M-96-D001 97-09-19
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
a APPLICATION DIAGRAM2 (ADC = L, SHL = H)
COM33 . . . COM32
LCD Panel (64 x 128)
SEG1 SEG2 .... SEG127 SEG128
COM1 . . . COM32
S128
C64 . . . C33
S127
...
S1
S1
C32 . . . C1
KS0708
(Top View)
*CS2B V0 V1 V2 V3 V4 V5 VEE E R/W RS DB[0:7] RESETB *CS1B CS1B
VDD 12 V0 V1 V2
*CS1B E R/W RS DB[0:7] RESETB
V3 V4
MPU V5
* Note When ADC = L, connects chip select pins(CS1B,CS2B) as following. - C1b (mpu) -> CS2B (KS0708) - CS2B (MPU) -> CS1B (KS0708) Figure 8. Application Diagram 2
VEE
M/M-96-D001 97-09-19
21
PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
a APPLICATION DIAGRAM3 (ADC = L, SHL = L)
VDD V0 V1 MPU V2 V3 V4 V5
E R/W RS DB[0:7] RESETB *CS2B *CS2B *CS1B C33 . . . . C64 COM1 . . COM32
12
E RW RS DB[0:7] RESETB
(Bottom View)
S128 S127 . . . S2 S1
SEG1 SEG2 .... SEG127 SEG128
LCD Panel (64 x 128)
*CS2B
KS0708
VEE V5 V4 V3 V2 V1 V0
VEE
C1 . . . . C32
COM33 . . COM64
* Note When ADC = L, connects chip select pins (CS1B, CS2B) as following. - CS1B (MPU) -> CS2B (KS0708) - CS2B (MPU) -> CS1B (KS0708)
Figure 9. Application Diagram 3
M/M-96-D001 97-09-19
22
PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
a APPLICATION DIAGRAM4 (ADC = H, SHL = L)
VDD V0 V1 MPU V2 V3 V4 V5
E R/W RS DB[0:7] RESETB *CS2B *CS2B *CS2B C1 . . . . C32 COM33 . . COM64
12
VEE
C33 . . . . C64
E RW RS DB[0:7] RESETB
*CS1B
KS0708
(Top View)
S128
VEE V5 V4 V3 V2 V1 V0
S1
S2 . . . S127
SEG1 SEG2 .... SEG127 SEG128
LCD Panel (64 x 128)
COM1 . . . COM32
Figure 10. Application Diagram 4
M/M-96-D001 97-09-19
23
PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
SPECIFICATIONS
Absolute Maximum Ratings
Parameter Operating voltage Supply Voltage Driver Sypply Voltage Symbol VDD VEE VB VLCD Rating -0.3 ~ +7.0 VDD-19.0 ~ VDD+0.3 -0.3 ~ VDD+0.3 VEE-0.3 ~ VDD+0.3 V Unit Note *1 *4 *1,3 *2
Note : *1. Based on Vss = 0V *2. VLCD = VDD - VEE *3. Applies to SHL, FS, PCLK2, CR, RESETB, ADC, CS1B, CS2B, E, RW, RS and DB0 ~ DB7. *4. Voltage level VDD A V0 A V1 A V2 A V3 A V4 A V5 A VEE
Temperature Characteristics
Parameter Operating temperature Storage temperature Symbol Topr Tstg Rating -30 ~ +85 E -55 ~ +125 Unit Note
M/M-96-D001 97-09-19
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
Electrical Characteristics
DC Characteristics
(VDD = 4.5 ~ 5.5V, Ta = -30 ~ +85 E) Item Operating Voltage Input High Voltage Symbol VDD VIH1 VIH2 VIL1 Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Tri-state Leakage Current Driver Input Leakage Current Operating Current
COM
Condition IOH = -200uA IOL = 1.6mA VIN = VSS ~ VDD VIN = VSS ~ VDD VIN = VEE ~ VDD During Display During Access VDD - VEE = 17V 3/4ILOAD = 0.1mA Ta=25E, VDD=5V Rf = 47k U 3/4 2% Cf = 20pF 3/4 5%
Min 4.5 0.7VDD 2.0 0 0 2.4 -1.0 -5.0 -10 315
Typ 450
Max 5.5 VDD VDD 0.3VDD 0.8 0.4 +1.0 +5.0 +10 0.8 1.0 1.5 7.5 585
Unit
Note
*1 *2 V *1 *2 *3 *4 uA *5 *6 *7 mA *8 *9 kU *10
VIL2 VOH VOL ILKG ITSL IDLKG IDD1 IDD2 RONC RONS fosc
On resistance
SEG
Oscillation frequency
KHz
Note : *1. FS, CR, ADC, SHL, PCLK2, RESETB *2. CS1B, CS2B, E, RW, RS, DB0 ~ DB7 *3. DB0 ~ DB7 *4. Excepted DB0 ~ DB7 *5. DB0 ~ DB7 at High Impedence *6. V0, V1, V2, V3, V4, V5 *7. C = 20pF, R = 47 k U, fose = 450 KHz, DB0 ~ DB7 = VDD, Output = No Load *8. Excepted Clock = 430KHz, RAM Access Cycle = 1MHz *9. V0 = 5V, V1 = 3.2V, V2 = 1.4V, V3 = -8.4V, V4 = -10.2V, V5 = -12V, C1 ~ C64 *10. V0 = 5V, V1 = 3.2V, V2 = 1.4V, V3 = -8.4V, V4 = -10.2V, V5 = -12V, S1 ~ S128
M/M-96-D001 97-09-19
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PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
AC Characteristics (VDD = 4.5 to 5.5V, Ta = -30 to +85 E) Mode Item E Cycle Time E Rise / Fail Time Write Mode (Refer to Figure 9) E Pulse Width(High, Low) RW and RS Setup Time RW and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time Read Mode (Refer to Figure 10) E Pulse Width (High, Low) Rw and Rs Setup Time RW and RS Hold Time Data Output Delay Time Data Hold Time Symbol tc tr, tf tw tsu1 th1 tsu2 th2 tc tr,tf tw tsu th tD tDH Min 1000 450 140 10 200 10 1000 450 140 10 20 Typ Max 25 25 320 ns ns Unit
M/M-96-D001 97-09-19
26
PRELIMINARY SPECIFICATION
KS0708
64COM/128SEG DRIVE FOR DOT MATRIX LCD
RS
VIH1 VIL1
tSU1 RW
VIL1
th1
VIL1
tw E tf DB0 ~ DB7
VIH1 VIL1 VIH1 VIL1 VIH1 VIL1
th1 tf
VIL1
tSU2 Valid Data
th2
VIH1 VIL1
tC
Figure 9. Write Mode Timing Diagram
RS
VIH1 VIL1
tSU
VIH1
th
VIH1
RW
tw
VIH1 VIL1 VIH1 VIL1
th tf
E
VIL1
tr
tD
VIH1 VIL1
tDH
VIH1 VIL1
DB0 ~ DB7
Valid Data
tc
Figure 10. Read Mode Timing Diagram
M/M-96-D001 97-09-19
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